A need may arise in many data, communications or other similar systems to switch between multiple asynchronous clocks, data signals or the like. Such switching typically is accomplished via multiplexers.
Many conventional multiplexer systems generate spurious signals or “glitches” at multiplexer outputs when the multiplexer systems switch between output signals. Glitches may generate false logic states within an integrated circuit, and may damage sensitive circuit devices. High frequency circuits are especially vulnerable as they may generate large, high frequency glitches that may mix to produce undesirable input or output tones.
Numerous approaches have been proposed for reducing glitches during switching, such as allowing a predetermined time to elapse after switching before a new signal is output (e.g., so that all output nodes of a multiplexer have time to stabilize), or using cascaded edge triggered latches to minimize meta-stability in a data path. Other proposed approaches that relate specifically to switching between clock signals include pulling an output node to a predetermined state in between clock transitions (regardless of the previous state of the output node), requiring a selected clock signal to reach a predetermined logic state before allowing switching, or using edge detection to detect a change in the selection of a specific clock. However, such approaches may result in substantial switching delays, be difficult or expensive to implement and/or fail as the frequency of signal selection increases.
Accordingly, a need exists for improved methods and apparatus for multiplexing signals.